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PRELIMINARY DATA SHEET
MICRONAS
MAS 3507D MPEG 1/2 Layer 2/3 Audio Decoder
Edition March 16, 2000 6251-459-3PD
MAS 3507D
Contents Page 5 5 6 6 6 7 7 7 8 8 8 8 8 9 9 9 9 9 10 11 11 11 12 12 12 13 13 13 13 14 14 15 15 16 Section 1. 1.1. 1.2. 1.2.1. 1.2.2. 2. 2.1. 2.2. 2.3. 2.4. 2.4.1. 2.4.2. 2.4.3. 2.5. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.6.4. 2.7. 2.7.1. 2.7.2. 2.7.3. 2.7.3.1. 2.7.3.2. 2.7.3.3. 2.7.3.4. 2.7.4. 2.7.4.1. 2.7.4.2. 2.7.4.3. 2.8. 2.8.1. 2.9. Title Introduction Features Application Overview Multimedia Mode Broadcast Mode Functional Description of the MAS 3507D DSP Core Firmware (Internal Program ROM) Program Download Feature Baseband Processing Volume Control / Channel Mixer Mute / Bypass Tone Control Bass / Treble Control Clock Management Power Supply Concept Internal Voltage Monitor DC/DC Converter Stand-by Functions Start-up Sequence Interfaces MPEG Bit Stream Interface (SDI) SDI* Selection Parallel Input Output Interface (PIO) PIO-DMA Input Mode Writing MPEG Data to the PIO-DMA DMA Handshake Protocol End of DMA Transfer Audio Output Interface (SDO) Mode 1: 16 Bits/Sample(I2S Compatible Data Format) Mode 2:32 Bit/Sample (Inverted SOI) Other Output Modes Start-up Configuration Parallel Input Output Interface (PIO) Status Pins in SDI Input Mode
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MAS 3507D
Contents, continued Page 18 18 18 19 19 20 20 20 21 21 21 21 22 22 22 22 23 23 23 23 23 24 24 24 24 25 25 25 26 26 28 28 30 30 30 31 32 33 33 34 35 36 37 37 Section 3. 3.1. 3.1.1. 3.2. 3.2.1. 3.2.2. 3.3. 3.3.1. 3.3.2. 3.3.3. 3.3.4. 3.3.5. 3.3.6. 3.3.7. 3.3.8. 3.3.9. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. 3.4.5. 3.4.6. 3.4.7. 3.4.8. 3.4.9. 3.4.10. 3.5. 3.6. 3.6.1. 3.6.2. 3.6.3. 3.7. 3.7.1. 3.7.1.1. 3.7.1.2. 3.7.1.3. 3.7.1.4. 3.7.1.5. 3.7.1.6. 3.7.2. 3.7.2.1. 3.7.2.2. 3.7.3. Title Control Interfaces I2C Bus Interface Device and Subaddresses Command Structure The Internal Fixed Point Number Format Conventions for the Command Description Detailed MAS 3507D Command Syntax Run Read Control Interface Data Write Register Write D0 Memory Write D1 Memory Read Register Read D0 Memory Read D1 Memory Default Read Protocol Description Run Command Read Control Interface Data Write to MAS 3507D Register Write to MAS 3507D D0 Memory Write to MAS 3507D D1 Memory Read Register Read D0 memory Read D1 memory Default Read Write Data to the Control Register Version Number Register Table DC/DC Converter Muting / Bypass Tone Control Bass and Treble Control Memory Area Status Memory MPEG Frame Counter MPEG Status 1 MPEG Status 2 CRC Error Counter Number Of Ancillary Bits Ancillary Data Configuration Memory PLL Offset for 44/48 kHz Sampling Frequency Output Configuration Baseband Volume Matrix
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Contents, continued Page 39 39 40 43 43 43 43 43 43 43 44 44 44 45 45 46 47 47 47 49 50 51 52 53 53 54 55 60 Section 4. 4.1. 4.2. 4.2.1. 4.2.1.1. 4.2.1.2. 4.2.1.3. 4.2.1.4. 4.2.1.4.1. 4.2.1.4.2. 4.2.1.5. 4.2.1.6. 4.2.1.7. 4.2.1.8. 4.2.2. 4.2.3. 4.2.4. 4.2.4.1. 4.2.4.2. 4.2.4.3. 4.2.4.3.1. 4.2.4.3.2. 4.2.4.3.3. 4.2.4.4. 4.2.4.4.1. 4.2.4.5. 4.2.4.6. 5. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins DC/DC Converter Pins Control Lines Parallel Interface Lines PIO Handshake Lines PIO Data Lines Voltage Supervision And Other Functions Serial Input Interface Serial Output Interface Miscellaneous Pin Configurations Internal Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics I2C Characteristics I2S Bus Characteristics - SDI I2S Characteristics - SDO Firmware Characteristics Input Timing Parameters of the MultimediaMode DC/DC Converter Characteristics Typical Performance Characteristics Data Sheet History
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MAS 3507D
1.1. Features - Serial asynchronous MPEG bit stream input (SDI) - Parallel (PIO-DMA) Input - Broadcast and multimedia operation mode - Automatic locking to given data rate in broadcast mode
MPEG 1/2 Layer 2/3 Audio Decoder Release Note: Revision bars indicate significant changes to the previous edition. This data sheet applies to MAS 3507D version G10 and following versions.
1. Introduction The MAS 3507D is a single-chip MPEG layer 2/3 audio decoder for use in audio broadcast or memory-based playback applications. Due to embedded memories, the embedded DC/DC up-converter, and the very low power consumption, the MAS 3507D is ideally suited for portable electronics. In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. Layer 2 (widely used in DVB, ADR, and DAB) achieves a compression of 8:1 providing CD quality. In order to achieve better audio quality at low bit rates (<64 kbit/s per audio channel), three additional sampling frequencies are provided by MPEG 2 (ISO 13818-3). The MAS 3507D decodes both layer 2 and layer 3 bit streams as defined in MPEG 1 and 2. The multichannel/multilingual capabilities defined by MPEG 2 are not supported by the MAS 3507D. An extension to the MPEG 2 layer 3 standard developed by FhG Erlangen, Germany sometimes referenced as MPEG 2.5, for extremely low bit rates at sampling frequencies of 12, 11.025, or 8 kHz is also supported by the MAS 3507D.
- Data request triggered by 'demand signal' in multimedia mode - Output audio data delivered (in various formats) via an I2S bus (SDO) - Digital volume / stereo channel mixer / Bass / Treble - Output sampling clocks are generated and controlled internally. - Ancillary data provided via I2C interface - Status information accessible via PIO pins or I2C - "CRC Error" and "MPEG Frame Synchronization" Indicators at Pins in serial input mode - Power management for reduced power consumption at lower sampling frequencies - Low power dissipation (30 mW @ fs 12 kHz, 46 mW @ fs 24 kHz, 86 mW @ fs > 24 kHz @ 2.7 V) - Supply voltage range: 1.0 V to 3.6 V due to built-in DC/DC converter (1-cell/2-cell battery operation) - Adjustable power supply supervision - Power-off function - Additional functionality achievable via download software (CELP voice Decoder, ADPCM encoder / decoder)
CLKI CLKO
MAS 3507D
Clock Synthesizer DC/DC Converter /3/
decoded output /3/
Serial Out I2S
RISC DSP Core
PIO
/8+5/
MPEG 1/2 audio bit stream /2/ Serial In
serial control I2C /2/
MPEG frame sync
CRC error
Fig. 1-1: MAS 3507D block diagram
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1.2. Application Overview The MAS 3507D can be applied in two major environments: in multimedia mode or in broadcast mode. For both modes, the DAC 3550A fits perfectly to the requirements of the MAS 3507D. It is a high-quality multi sample rate DAC (8 kHz ... 50 kHz) with internal crystal oscillator, which is only needed for generating the decoder clock, and integrated stereo headphone amplifier plus 2 stereo inputs.
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A delayed response of the host to the demand signal (by several milliseconds) or an interrupted response of the host will be tolerated by the MAS 3507D as long as the input buffer does not run empty. A PC might use its DMA capabilities to transfer the data in the background to the MAS 3507D without interfering with its foreground processes. The source of the bit stream may be a memory (e.g. ROM, Flash) or PC peripherals, such as CD-ROM drive, an ISDN card, a hard disk or a floppy disk drive.
1.2.1. Multimedia Mode 1.2.2. Broadcast Mode In a memory-based multimedia environment, the easiest way to incorporate a MAS 3507D decoder is to use its data-demand pin. This pin can be used directly to request input bit stream data from the host or memory system. While the demand pin is active, the data stream shall be transmitted to the MAS 3507D. The bit stream clock should be higher than the actual data rate of the MPEG bit stream (1 MHz bit stream clock works with all MPEG bit rates). The demand signal will be active until the input buffer of the MAS 3507D is filled. In environments where the bit stream is delivered from an independent transmitter to one or more receivers, the MAS 3507D cannot act as master for the bit stream clock. In this mode, it synchronizes itself to the incoming bit stream data rate by a digital PLL and generates a synchronized digital audio sample clock for the required output sample rates.
I2C demand signal demand clock MPEG bit stream I2S
14.725 MHz line out
Host (PC, Controller)
MAS 3507D
DAC 3550A
CLKI ROM, CD-ROM, RAM, Flash Mem. ..
CLKOUT
Fig. 1-2: Block diagram of a MAS 3507D, decoding a stored bit stream in multimedia mode
control I2C L3 bit stream (fixed rate)
2
14.725 MHz IS
Receiver Front-end
MAS 3507D
DAC 3550A
line out
clock
CLKI
CLKOUT
Fig. 1-3: Block diagram of a MAS 3507D in a broadcast environment
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MAS 3507D
2.2. Firmware (Internal Program ROM) A valid MPEG 1/2/2.5 layer 2/3 data signal is taken as input. The signal lines are a clock line SIC and the data line SID. The MPEG decoder performs the audio decoding. The steps for decoding are - synchronization, - side information extraction, - audio data decoding, - ancillary data extraction, and - volume and tone control. For the supported bit rates and sample rates, see Table 3-12 on page 32. Frame synchronization and CRC-error signals are provided at the output pins of the MAS 3507D in serial input mode.
2. Functional Description of the MAS 3507D 2.1. DSP Core The hardware of the MAS 3507D consists of a high performance RISC Digital Signal Processor (DSP) and appropriate interfaces (see Fig. 2-1). The internal processor works with a memory word length of 20 bits and an extended range of 32 bits in its accumulators. The instruction set of the DSP is highly optimized for audio data compression and decompression. Thus, only very small areas of internal RAM and ROM are required. All data input and output actions are based on a `non cycle stealing' background DMA that does not cause any computational overhead.
MPEG Bit Stream
Sync
Ancillary Data
Digital Audio Output
Volume Tone Control
MPEG Decoder
Decoder Status
to C
Config. Reg.
PIO
Status
Start-up Config.
Fig. 2-1: Block diagram of the MPEG Decoder in serial input mode
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2.3. Program Download Feature This is an additional feature that is not required for the MPEG decoding function. The overall function of the MAS 3507D can be altered by downloading up to 1 kWord program code into the internal RAM and executing this code instead of the ROM code. During this time, MPEG decoding is not possible. The code must be downloaded by the `write to memory' command (see Section 3.3.) into an area of RAM that is switchable from data memory to program memory. A `run' command (see Section 3.3.1.) starts the operation. Micronas provides modules for voice-decoding using the CELP algorithm (performing good speech quality at very low bit rates) and for encoding and decoding audio data with ADPCM. Detailed information about downloading is provided in combination with the MAS 3507D software development package from Micronas. For commercial issues and detailed information please contact our sales department.
PRELIMINARY DATA SHEET
2.4. Baseband Processing 2.4.1. Volume Control / Channel Mixer A digital volume control matrix is applied to the digital stereo audio data. This performs additional balance control and a simple kind of stereo basewidth enhancement. The 4 factors LL, LR, RL, and RR are adjustable via the controller with 20-bit resolution. See Fig. 3-2 and Section 3.7.3. for details.
2.4.2. Mute / Bypass Tone Control A special bit enables a fast and simple mute functionality without changing the current volume setting. Another bit allows to bypass the complete bass / treble / volume control. See for details Section 3.6.2.
2.4.3. Bass / Treble Control Tone control is implemented in the MAS 3507D. It allows the control of bass and treble in a range up to 15 dB, as Table 3-9 shows. To prevent overflow or clipping effects, the prescaler is built-in. The prescaler decreases the overall gain of the tone filter, so the full range up to +15 dB is usable without clipping. Due to the different frequency ranges in MPEG 1, MPEG 2, or MPEG 2.5, the bass cutoff frequencies differ. Table 2-1: Cutoff Frequencies Cutoff MPEG 1 MPEG 2 MPEG 2.5 Bass 100 Hz 200 Hz 400 Hz Treble 10 kHz 10 kHz 10 kHz
For details see Section 3.6.3..
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MAS 3507D
2.6.2. DC/DC Converter The DC/DC converter of the MAS 3507D is used to generate a fixed power supply voltage even if the chip set is powered by battery cells in portable applications. The DC/DC converter is designed for the application of 1 or 2 batteries or NiCd cells as shown in Fig. 2-3 which shows the standard application circuit. The DC/ DC converter is switched on by activating the DCEN pin. Its output power is sufficient for other ICs as well. Note: Connecting DCEN directly to VDD leads to unexpected states of the DCCF register. The PUP signal should be read out by the system controller. A 22 H inductor is required for the application. The important specification item is the inductor saturation current rating, which should be greater than 2.5 times the DC load current. The DC resistance of the inductor is important for efficiency. The primary criterion for selecting the output filter capacitor is low equivalent series resistance (ESR), as the product of the inductor current variation and the ESR determines the high-frequency amplitude seen on the output voltage. The Schottky diode should have a low voltage drop VD for a high overall efficiency of the DC/DC converter. The current rating of the diode should also be greater than 2.5 times the DC output current. The VSENS pin has to be always connected to the output voltage.
2.5. Clock Management The MAS 3507D should be driven by a single clock at a frequency of 14.725 MHz. It is possible to drive the MAS 3507D with other reference clocks (see Section 3.7.2.1. on page 36). The CLKI signal acts as a reference for the embedded clock synthesizer that generates the internal system clock. Based on the reference input clock CLKI, a synchronized output clock CLKO that depends on the audio sample frequency of the decompressed bit stream is generated and provided as `master clock' to external D/A converters. Some of them need master clocks that have a fixed relation to the sampling frequencies. A scaler can be switched on during start-up, optionally, by setting the PI8 pin to 0. Then, the clock-out will automatically be divided by 1, 2, or 4 as defined in Table 2-2. Table 2-2: CLKO Frequencies fs/kHz 48, 32 44.1 24, 16 22.05 12, 8 11.025 CLKO/MHz scaler on 24.576 22.5792 12.288 11.2896 6.144 5.6448 CLKO/MHz scaler off 24.576 22.5792 24.576 22.5792 24.576 22.5792
2.6.3. Stand-by Functions The digital part of the MAS 3507D and the DC/DC converter are turned on by setting WSEN. If only the DC/DC converter should work, it can remain active by setting DCEN alone to supply other parts of the application even if the audio decoding part of the MAS 3507D is not being used. The WSEN power-up pin of the digital part may be handled by the controller. Please pay attention to the fact, that I2C protocol is working only if the processor and its interfaces works (WSEN = 1)
2.6. Power Supply Concept The MAS 3507D offers an embedded controlled DC/ DC converter for battery based power supply concepts. It works as an up-converter.
2.6.1. Internal Voltage Monitor An internal voltage monitor compares the input voltage at the VSENS pin with an internal reference value that is adjustable via I2C bus. The PUP output pin becomes inactive when the voltage at the VSENS pin drops below the programmed value of the reference voltage. It is important that the WSEN must not be activated before the PUP is generated. The PUP signal thresholds are listed in Table 3-8. The internal voltage monitor will be activated with a high level at Pin DCEN.
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2.6.4. Start-up Sequence The DC/DC converter starts from a minimum input voltage of 0.9 V. There should be no output load during startup. In case WSEN is active, the MAS 3507D is in the DSP operation mode. The start-up script should be as follows: 1. Enable the DC/DC-converter with a high signal (VDD, AVDD) at pin DCEN. 2. Wait until PUP goes "high". 3. Wait one more millisecond to guarantee that the output voltage has settled (recommended). 4. Enable the MAS 3507D with a "high" signal at pin "WSEN". Please also refer to Figure 2-2. > 0.9 V DCEN button Controller
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DSP operation =1 WSEN > 2 V DC/DC On
Fig. 2-2: DC/DC operation
CLKI
VDD
AVDD DCSO
optional filter
22 H
Start-up oscillator Frequency divider
64...94 x2 32...47 +32 0...15 DCCF $8e 9 10 16
DCSG
DC/DC converter
DCEN Power-On Push Button
+ -
Cout 330 F Low ESR
voltage monitor
Cin 330 F
+ -
PUP WSEN VSENSE 10 k
Vin 0.9 V
VSS
AVSS
10 nF
47 k 47 k
Controller Fig. 2-3: DC/DC converter connections
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The MPEG input signal format is shown in Fig. 2-4. The data values are latched with the falling edge of the SIC signal. The MPEG bit stream generated by an encoder is unformatted. It will be formatted (e.g. 8 bit or 16 bit) by storing on a media (Flash-RAM, Harddisk). The serial data required from the MPEG bit stream interface must be in the same bit order as produced by the encoder.
2.7. Interfaces The MAS 3507D uses an I2C control interface, 2 selectable serial input interfaces for MPEG bit stream (SDI, SDI*) , a parallel I/O interface (PIO) for MPEG- or ADPCM-data and a digital audio output interface (SDO) for the decoded audio data (I2S or similar). Additionally, the parallel I/O interface (PIO) may be used for monitoring and mode selection tasks. The PIO lines are defined by the internal firmware.
2.7.2. SDI* Selection 2.7.1. MPEG Bit Stream Interface (SDI) The MPEG bit stream input interface uses the three pins: SIC, SII, and SID. For MPEG decoding operation, the SII pin must always be connected to VSS. The serial interface has to be initialized before the first use. Otherwise no output signal is produced. After Power-up or a rising slope on Pin PORQ, write the following I2C-command, while SIC is hold low: W $3A 68 93 B0 00 02 (write $0020 into register $3B) W $3A 68 00 01 (execute "RUN 1" command) An alternative serial input (SDI*) is available. The alternative serial input can be selected by setting register SI1M0 at address $4f (see Table 2-3). Table 2-3: SDI* Selection via Register SI1M0, $4f (write) Value 0 2 Function use SDI lines use PI14...PI16 pins for serial input (named SDI*)
Vh
SIC
Vl
Vh
data valid latch data at falling edge of clock
SII
Vl
Vh
SID
Vl
Fig. 2-4: Schematic timing of the SDI (MPEG) input
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2.7.3. Parallel Input Output Interface (PIO) The parallel interface of the MAS 3507D uses the lines PI0...PI4, PI8, PI12...PI19, and several control lines.
PRELIMINARY DATA SHEET
. Table 2-4: Switching from SDI- to PIO-DMA-Input Address 1) $e6, Bit 4 Value 1
2.7.3.1. PIO-DMA Input Mode By setting the PIO pin PI4 to "1", the PIO-DMA input mode of the MAS 3507D is activated after reset. Normally, the input mode should not be altered in a customer's application. Should this nonetheless be desired, the necessary changes are described in Table 2-4 and Table 2-5.
1)
Startup Configuration Register
Table 2-5: Switching from PIO-DMA- to SDI-Input Step 1 Address 1) $e6, Bit 4 $4b Value 0 $82
2.7.3.2. Writing MPEG Data to the PIO-DMA The PIO-DMA mode enables the writing of 8-bit parallel MPEG data to the MAS 3507D. In this mode, PIO lines PI19...PI12 are switched to the MAS 3507D data input which hence will be an 8-bit parallel input port with MSB first (at position PI19) for the MPEG bit stream data. In order to write data to this parallel port successfully, a special handshake protocol has to be used by the controller (see Fig. 2-5). Note: Either SII has to be set to "1", or SIC clock input has to be stopped ("0") in this mode.
2
1)
PIO Configuration Register Note: These 2 steps must be done in above order!
.
tst tr tpd trtrq trpr teod teodq
high
EOD
tpr
low high low high
PR
RTR
tset th
low high low Byte 15
MAS 3507D latches the PIO DATA
PI[19:12]
Byte 1
Fig. 2-5: Handshake protocol for writing MPEG data to the PIO-DMA
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Table 2-6: PIO DMA Timing Symbol tst tr tpd tset PIO Pin PR, EOD PR, RTR PR, PI[19:12] PI[19:12] PI[19:12] RTR PR PR, RTR PR, EOD EOD Min. 0.010 40 120 160 160 200 120 40 40 0 Max. 2000 160 480 no limit no limit 30000 no limit no limit 160 500 Unit s ns ns ns ns ns ns ns ns s
2.7.3.3. DMA Handshake Protocol The data transfer can be started after the EOD pin of the MAS 3507D is set to "high". After verifying this, the controller signalizes the sending of data by activating the PR line. The MAS 3507D responds by setting the RTR line to the "low" level. The MAS 3507D reads the data PI[19:12] tpd ns after rising edge of the PR. The next data word write operation will again be initialized by setting the PR line via the controller. Please refer to Figure 2-5 and Table 2-6 for the exact timing
2.7.3.4. End of DMA Transfer The above procedure will be repeated until the MAS 3507D sets the EOD signal to "0", which indicates that the transfer of one data block has been executed. Subsequently, the controller should set PR to "0", wait until EOD rises again, and then repeat the procedure (see Section 2.7.3.3. ) to send the next block of data. The DMA buffer is 15 bytes long. The recommended PIO-DMA conditions and the characteristics of the PIO timing are given in Table 2-6
th trtrq tpr trpr teod teodq
2.7.4. Audio Output Interface (SDO) The audio output interface of the MAS 3507D is a standard I2S interface. It is possible to choose between two standard interfaces (16 bit with delay or 32 bit without delay and inverted SOI) via start-up configuration. These setup modes meet the performance of the most common DACs. It is also possible to select other interface modes via I2C commands (see Section 2.7.4.3.). .
2.7.4.1. Mode 1: 16 Bits/Sample (I2S Compatible Data Format) A schematic timing diagram of the SDO interface in 16 bit/sample mode is shown in Fig. 2-6.
Vh
SOC
Vl
Vh
SOD
15 14 13 12 11 10 9 8
Vl
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
76543210
SOI
Vh Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 2-6: Schematic timing of the SDO interface in 16 bit/sample mode
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2.7.4.2. Mode 2:32 Bit/Sample (Inverted SOI) If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default (see Fig. 2-7) The 12 trailing bits for left and right channel of the SDO interface can be accessed by writing to registers as shown in Table 2-7. Table 2-7: Access for Trailing Bits Register $c5 $c6 Bit 0 ... 11 Left Channel Right Channel
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2.7.4.3. Other Output Modes The interface is also configurable by software to work in different modes. It is possible to choose: - 16 or 32 bit/sample modes, - inverted or noninverted word strobe (SOI), - no delay or delay of data related to word strobe - inverted or noninverted I2S-Clock (SOC). For further details see Section 3.7.2.2.
Vh
SOC
Vl
...
...
Vh
SOD
Vl
31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 ... 7 6 5 4 3 2 1 0
Vh
SOI
Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 2-7: Schematic timing of the SDO interface in 32 bit/sample mode
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2.8. Start-up Configuration Basic operation of the MAS 3507D is possible without controller interaction. Configuration and the most important status information are available by the PIO interface. The start-up configuration is selected according to the levels of several PIO pins. The levels should be set via high impedance resistors (for example 10 k) to VSS or VDD and will be copied into the StartupConfig register directly after power up / reset. After start-up, the PIO will be reconfigured as output. To enable greater flexibility, it is possible to configure the MAS 3507D without using the PIO pins or to reconfigure the IC after start-up. The procedure for this is to send two I2C commands to the MAS 3507D: - Writing the StartupConfig register (see Section 3.6. on page 26) - Execute a `run $0fcd' command (see Section 3.3.1.). The configuration will be active up to a reset. Then, the new configuration will be loaded again via PIO.
Table 2-8: Start-up configuration1) PIO Pin PI8 "0" divide CLKO by 1, 2, or 4 (according to MPEG 1, 2, or 2.5) SDI input mode Enable layer 3 Enable layer 2 SDO output: 32 bit input: Multimedia mode (PLL off) "1" CLKO fixed at 24.576 or 22.5792 MHz PIO-DMA input mode Disable layer 3 Disable layer 2 SDO output: 16 bit input: Broadcast mode (PLL on)
PI4 PI3 PI2 PI1 PI0
1) Start-up setting can be changed by I2C commands after reset.
2.8.1. Parallel Input Output Interface (PIO) During start-up, the PIO will read the start-up configuration. This is to define the environment for the MAS 3507D. The following pins must be connected via resistors to VSS or VDD:
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2.9. Status Pins in SDI Input Mode After having read the start-up configuration, the PIO will be switched to `P-mode'. In P-mode, the additional PIO control lines (PR, PCS) are evaluated. If the MPEG decoder firmware detects PR = `1' and the PCS = `0'. Then, all PIO interface lines are configured as output and display some status information of the MPEG decoder. The PIO lines can be read by an external controller or directly used by dedicated hardware blocks (e.g. for sample rate indication or display units). The internal MPEG decoder firmware attaches specific functions to the following pins. The MPEG-FRAME-SYNC signal is set to `1' after the internal decoding for the MPEG header has been finished for one frame. The rising edge of this signal could be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. As soon as the MAS 3507D has recognized the corresponding read command (`read control interface data' (see Section 3.3.2. on page 21), the MPEG-FRAME-SYNC is reset. This behavior reduces the possibility of missing the MPEG-FRAME-SYNC active state. tframe=24 ... 72 ms tread
Vh
l
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Table 2-9: PIO output signals during MPEG decoding in SDI mode PIO Pin PI19 Name Demand PIN %0 %1 PI18, PI17 MPEG INDEX %00 %01 %10 %11 MPEG Layer ID %00 %01 %10 %11 MPEG CRC-ERROR %0 %1 no error CRC-error, MPEG decoding not successful see following text in kHz2) 44.1 / 22.1 / 11.0 48 / 24 / 12 32 / 16 / 8 reserved reserved Layer 3 Layer 2 Layer 11) MPEG 2.5 reserved MPEG 2 MPEG 1 no input data exp. input data request Comment
PI13, PI12
PI8
PI4 PI3, PI2
MPEG-FRAMESYNC Sampling frequency %00 %01 %10 %11 Deemphasis %00 %01 %10 %11
MPEG-FRAME-SYNC Fig. 2-8: Schematic timing of MPEG-FRAME-Sync
The time tread depends on the response time of the controller. This time must not exceed 1/2 of the MPEGframe length tframe. The MPEG frame lengths are given in Table 2-10
PI1, PI0
none 50/15 s reserved CCITT J.17
1) 2)
Layer 1 bit streams will not be decoded Sampling frequency also defined by MPEG index (see Table 3-12 for additional information)
.
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MAS 3507D
Table 2-10: Frame length in MPEG layer 2 / 3 fs in kHz 48 44.1 32 24 22.05 16 12 11.025 8 Frame Length Layer 2 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 32 ms not available not available not available Frame Length Layer 3 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 32 ms 48 ms 52.24 ms 72 ms
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MAS 3507D
3. Control Interfaces 3.1. I2C Bus Interface 3.1.1. Device and Subaddresses The MAS 3507D is controlled via the I2C bus slave interface. The IC is selected by transmitting the MAS 3507D device addresses. (see Table 3-1). Writing is done by sending the device write address, ($3a) followed by the subaddress byte ($68), two or more bytes of data. Reading is done by sending the write device address ($3a), followed by the subaddress byte ($69). Without sending a stop condition, reading of the addressed data is completed by sending the device read address ($3b) and reading n-bytes of data.
PRELIMINARY DATA SHEET
By means of the RESET bit in the CONTROL register, the MAS 3507D can be reset by the controller. Due to the internal architecture of the MAS 3507D, the IC cannot react immediately to an I2C request. The typical response time is about 0.5 ms. If the MAS 3507D cannot accept another complete byte of data until it has performed some other function (for example, decoding MP3 data), it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by 'Wait' in section 3.4. The maximum wait period of the MAS 3507D during normal operation mode is less than 4 ms. Table 3-1: I2C Bus Device Addresses MAS 3507D Device Address MAS_I2C_ADR Write $3a Read $3b
Table 3-2: I2C Bus Subaddresses Name CONTROL_MAS WR_MAS RD_MAS Binary Value 0000 0000 0110 1000 0110 1001 Hex Value $6a $68 $69 Mode Write Write Write Function control subaddress (see Table 3-3) write subaddress read subaddress
Table 3-3: Control Register (Subaddress: $6a) Name CONTROL Subaddress $6a Bit : 8 1 : Reset 0 : normal Bit : 0-7, 9-15 0
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PRELIMINARY DATA SHEET
MAS 3507D
Note: S = P= ACK = NAK = Wait =
I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave or master Not Acknowledge-Bit: HIGH on I2C_DA from master to indicate `End of Read' I2C-Clock line is held low, while the MAS 3507D is processing the I2C command.
I2C_DA S I2C_CL
1 0 P
Fig. 3-1: I2C bus protocol (MSB first; data must be stable while clock is high)
3.2. Command Structure The I2C control of the MAS 3507D is done completely via the I2C data register by using a special command syntax. The commands are executed by the MAS 3507D during its normal operation without any loss or interruption of the incoming data or outgoing audio data stream. These I2C commands allow the controller to access internal states, RAM contents, internal hardware control registers, and even a download of an alternative software module. The command structure allows sophisticated control of the MAS 3507D. The registers of the MAS 3507D are either general purpose, e.g. for program flow control, or specialized registers that directly affect hardware blocks. The unrestricted access to these registers allows the system controller to overrule the firmware configuration of the serial interfaces or the default input line selection. The control interface is also used for low bit rate data transmission, e.g. MPEG-embedded ancillary data transmission. The data information is performed by sending a `read memory' command to the MAS 3507D and by reading the memory block that temporarily contains the required information. The synchronization between the controller and the MAS 3507D is done via a MPEG-FRAME-SYNC signal or by monitoring the MPEGFrameCount register (at the cost of a higher work load for the controller). The MAS 3507D firmware scans the I2C interface periodically and checks for pending or new commands. However, due to some time critical firmware parts, a certain latency time for the response has to be expected. The theoretical worst case response time does not exceed 4 ms. Table 3-4 shows the basic controller commands that are available by the MAS 3507D.
3.2.1. The Internal Fixed Point Number Format Internal register or memory values can easily be accessed via the I2C interface. In this document, two number representations are used: the fixed point notation `v' and the 2's complement number notation `r'. The conversion between the two forms of notation is easily done (see the following equations). r = v x 524288.0 + 0.5; (-1.0 v < 1.0) v = r / 524288.0; (-524288 < r < 524287) (EQ 1) (EQ 2)
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MAS 3507D
3.2.2. Conventions for the Command Description The description of the various controller commands uses the following formalism: - A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant nibble. - Data values in nibbles are always shown in hexadecimal notation indicated by a preceding $. - A hexadecimal 20-bit number d is written, e.g. as d = $17C63, its five nibbles are d0 = $3, d1 = $6, d2 = $C, d3 = $7, and d4 = $1. - Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don't care - Variables used in the following descriptions: dev_write $3a dev_read $3b data_write $68 data_read $69 control $6a
PRELIMINARY DATA SHEET
3.3. Detailed MAS 3507D Command Syntax 3.3.1. Run S
dev_write
A
data_write
A
a3,a2
A
a1,a0
AP
The `run' command causes the start of a program part at address a = (a3,a2,a1,a0). The nibble a3 is restricted to $0 or $1 which also acts as command selector. Run with address a = $0 will suspend normal MPEG decoding and only I2C commands are evaluated. This freezing will be required if alternative software is downloaded into the internal RAM of the MAS 3507D. Detailed information about downloading is provided in combination with a MAS 3507D software development package or together with MAS 3507D software modules available from Micronas. If the address $1400 a < $1800, the MAS 3507D continues execution of the program with the downloaded code. For detailed information, please refer to the MASC software development kit. This is for starting the downloaded program code. Example 1: `run' at address $fcd (override start-up configuration) has the following I2C protocol:
<$3a><$68><$0f><$cd>
Example 2: `run' at address $475 (activate PLLOffset and OutputConfig after change by write command) has the following I2C protocol:
<$3a><$68><$04><$75>
Table 3-4: Basic controller commands Code $0 $1 $3 $9 $A $B $D $E $F Command run read Control Information and Ancillary Data write register write to memory read register read memory Comment Start execution of an internal program. (Run 0 means freeze operating system.) fast read of a block of information organized in 16-bit words (see Section 3.7.1. on page 30) An internal register of the MAS 3507D can be written directly to by the controller. A block of the DSP memory can be written to by the controller. This feature may be used to download alternate programs. The controller can read an internal register of the MAS 3507D. A block of the DSP memory can be read by the controller.
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PRELIMINARY DATA SHEET
MAS 3507D
act with built-in hardware blocks. A list of useful registers is given in the next section. Example: Muting can be realized by writing the value 1 into the register with the number $aa:
<$3a><$68><$9a><$a1><$00><$00>
dev_read d3, d2
3.3.2. Read Control Interface Data
1) send command
S
dev_write
A
data_write
AS
$3, x2
A
x1,x0
AP
2) get ancillary data values
S
dev_write
A
AS (ancillary word 0) A
data_read
A A
d1,d0
3.3.4. Write D0 Memory
Nak
....repeat for n data values....
A
x2...x0: combined count, offset value d3...d0: 16-bit data values
d3, d2
d1,d0
P
S
dev_write
A
data_write
An internal memory array keeps the status information of the MAS 3507D (see Table 3-10). The `read control interface data' command can be used for quick access to this memory array. A successive range of memory locations may be read by passing a 6-bit offset value "o" and a 6-bit count value "n" as parameter. Both values are combined in a 12-bit = 4 nibble field x2, x1, x0. If, for example, 4 words (n = 4) starting with one word offset (o = 2), i.e. the MPEG Status 2, the CRCErrorCount, and NumberOfAncillaryBits are read from the control memory array, the 3 nibbles x2, x1 and x0 are evaluated as shown in the following table.
A A A A A A A
$A, $0 n3,n2 a3,a2 d3,d2 n3,n2 $0,$0
A A A A A A A
$0,$0 n1,n0 a1,a0 d1,d0 $0,d4
....repeat for n data values.... d3,d2 n3,n2 $0,$0 d1,d0 $0,d4
AP
n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value
The MAS 3507D has 2 memory areas of 2048 words each called D0 and D1 memory. For both memory areas, read and write commands are provided. Example: reconfiguration of the output to 16 bit without delay has the following I2C protocol:
<$3a><$68><$a0><$00> <$00><$01> <$03><$2f> <$00><$10> <$00><$00> <$3a><$68><$04><$75> (write D0 memory) (1 word to write) (start address) (value = $00010) (run command)
11 6-bit values bit nibble
10
9
8
7
6
5
4
3
2
1
0
offset: 2 0 0 0 0 0 1 8 0
number of words: 3 0 0 0 3 0 1 1
The complete I2C protocol reads as: 3.3.5. Write D1 Memory
<$3a><$68><$30><$83> <$3a><$69><$3b>
The `read control interface data' command resets the MPEG-FRAME-SYNC at PI4 pin (see Section 2.9. on page 16).
S
dev_write
A
data_write
3.3.3. Write Register S
dev_write
A A A A A A A
$B, $0 n3,n2 a3,a2 d3,d2 n3,n2 $0,$0
A A A A A A A
$0,$0 n1,n0 a1,a0 d1,d0 $0,d4
....repeat for n data values.... d3,d2 n3,n2 $0,$0 d1,d0 $0,d4
A
data_write
A
$9, r1 d4, d3
A A
r0, d0 d2, d1
A AP
AP
n3..n0: number of words to be transmitted a3..a0: start address in MASD memory d4..d0: data value
The controller writes the 20-bit value (d = d4,d3,d2,d1,d0) into the MAS 3507D register (r = r1,r0). In contrast to memory cells, registers are always addressed individually, and they may also inter-
For further details, see `write D0 memory' command.
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MAS 3507D
3.3.6. Read Register
1) send command
PRELIMINARY DATA SHEET
3.3.8. Read D1 Memory
1) send command
S S
dev_write
A A
data_write
A
$D, r1
A
r0,$0
AP
S
dev_write
A
data_write
2) get register value
dev_write data_read
A
d3, d2
A
d1,d0
AS A
dev_read X,X
A A A
$F, $0 n3,n2 a3,a2
A A A
$0,$0 n1,n0 a1,a0
AP
A
X, d4
Nak
P
2) get memory value
r1, r0: register r d3...d0: data value in r X: don't care
S
dev_write
A
data_read
A A
d3, d2
A A
d1,d0
AS A A
dev_read $0,$0
A A
$0, d4
....repeat for n data values.... d3, d2 d1,d0 $0,$0 $0, d4
NaK P
The MAS 3507D has an address space of 256 registers. Some of the registers (r = r1,r0 in the figure above) are direct control inputs for various hardware blocks, others do control the internal program flow. In the next section, those registers that are of any interest with respect to the MPEG decoding are described in detail. Example: Read the content of the PIO data register ($c8):
<$3a><$68><$dc><$80> <$3a><$69><$3b> now read:
n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value
The `read D1 memory' command is provided to get information from memory cells of the MAS 3507D. It gives the controller access to all memory cells of the internal D1 memory.
3.3.9. Default Read S
dev_write
A
data_read
AS A
device_read d3,d2
A
d1,d0
Nak
P
3.3.7. Read D0 Memory
1) send command
S
dev_write
A
data_write
A A A
$E, $0 n3,n2 a3,a2
A A A
$0,$0 n1,n0 a1,a0
AP
2) get memory value
The `default read' command immediately returns the content of the MPEGFrameCount (D0:$300) of the MAS 3507D in the variable (d = d3,d2,d1,d0). The `default read' command is the fastest way to get information from the MAS 3507D. Executing the `default read' command in a polling loop can be used to detect the availability of new ancillary data.
S
dev_write
A
data_read
A A
d3, d2
A A
d1,d0
AS A A
dev_read $0,$0
A A
$0, d4
....repeat for n data values.... d3, d2 d1,d0 $0,$0 $0, d4
NaK P
n3..n0: number of words a3..a0: start address in MASD memory d4..d0: data value
The `read D0 memory' command is provided to get information from memory cells of the MAS 3507D. It gives the controller access to all memory cells of the internal D0 memory. Direct access to memory cells is an advanced feature of the DSP. It is intended for users of the MASC software development kit.
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PRELIMINARY DATA SHEET
MAS 3507D
3.4. Protocol Description 3.4.1. Run Command
S $3A ACK $68 ACK a3, a2 ACK a1, a0 Wait ACK P
3.4.2. Read Control Interface Data Send Command
S $3A ACK $68 ACK $3, x2 ACK x1, x0 Wait ACK P
Get Ancillary Data Values
S $3A ACK $69 ACK S ACK $3B d3, d2 Wait ACK d1, d0 Wait
.... repeat for n data values ACK d3, d2 ACK d1, d0 Wait Nak P
3.4.3. Write to MAS 3507D Register
S $3A ACK $68 ACK $9,r1 d4,d3 ACK ACK r0,d0 d2,d1 Wait ACK Wait ACK P
3.4.4. Write to MAS 3507D D0 Memory
S $3A ACK $68 ACK ACK ACK ACK ACK $A, $0 n3, n2 a3, a2 d3, d2 $0, $0 ACK ACK ACK ACK ACK $0, $0 n1, n0 a1, a0 d1, d0 $0, $d4 Wait Wait Wait Wait Wait
.... repeat for n data values ACK ACK d3, d2 $0, $0 ACK ACK d1, d0 $0, $d4 Wait Wait Ack P
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MAS 3507D
3.4.5. Write to MAS 3507D D1 Memory
S $3A ACK $68 ACK ACK ACK ACK ACK $B, $0 n3, n2 a3, a2 d3, d2 $0, $0 ACK ACK ACK ACK ACK $0, $0 n1, n0 a1, a0 d1, d0 $0, $d4 Wait Wait Wait Wait Wait
PRELIMINARY DATA SHEET
.... repeat for n data values ACK ACK d3, d2 $0, $0 ACK ACK d1, d0 $0, $d4 Wait Wait Ack P
3.4.6. Read Register Send command
S $3A ACK $68 ACK $D, r1 ACK r0, $0 Wait ACK P
Get register value
S $3A ACK $69 ACK S ACK ACK $3B d3, d2 X, X Wait ACK ACK d1, d0 X, d4 Wait Wait Nak P
3.4.7. Read D0 memory Send Command
S $3A ACK $68 ACK ACK ACK $E, $0 n3, n2 a3, a2 ACK ACK ACK $0, $0 n1, n0 a1, a0 Wait Wait Wait ACK P
Get memory values
S $3A ACK $69 ACK S ACK $3B d3, d2 Wait ACK d1, d0 Wait ACK $0, $0 ACK $0, d4 Wait
.... repeat for n data values ACK d3, d2 ACK d1, d0 Wait ACK d3, d2 ACK d1, d0 Wait Nak P
3.4.8. Read D1 memory Send Command
S $3A ACK $68 ACK ACK ACK $F, $0 n3, n2 a3, a2 ACK ACK ACK $0, $0 n1, n0 a1, a0 Wait Wait Wait ACK P
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PRELIMINARY DATA SHEET
MAS 3507D
Get memory values
S $3A ACK $69 ACK S ACK $3B d3, d2 Wait ACK d1, d0 Wait ACK $0, $0 ACK $0, d4 Wait
.... repeat for n data values ACK d3, d2 ACK d1, d0 Wait ACK d3, d2 ACK d1, d0 Wait Nak P
3.4.9. Default Read
S $3A ACK $69 ACK S ACK $3B d3, d2 Wait ACK d1, d0 Wait Nak P
3.4.10.Write Data to the Control Register
S $3A ACK $6A ACK d3, d2 ACK d1, d0 Wait ACK P
3.5. Version Number Table 3-5 shows where the MAS 3507D hardware version, its software and additional information is located. Table 3-5: MAS 3507D Version Addr. D1:$ff6 Content name of MAS 3507D version hardware/software design code MAS 3507D F10 description: "MPEG 1/2.5 L23" Example Value 0x03507 3507
D1:$ff7
0x00601 (increases for new versions) 0x04d50 0x04547 0x02031 0x02f32 0x02e35 0x0204C 0x03233
0601
D1:$ff9 D1:$ffa D1:$ffb D1:$ffc D1:$ffd D1:$ffe D1:$fff
MP EG 1 /2 .5 L 23
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MAS 3507D
3.6. Register Table In Table 3-6, the internal registers that are useful for controlling the MAS 3507D are listed. They are accessible by `register read/write' I2C commands (see Section 3.3. on page 20). Important note! Writing into undocumented registers or read-only registers is always possible, but it is highly recommended not to do so. It may damage the function of the firmware and may even lead to a complete system crash of the decoder operation which can only be restored by a reset. Table 3-6: Command Register Table Address $8e $aa $ed1) R/W w r/w r Name DCCF Mute / Bypass Tone Control PIOData Comment Set DC/DC converter mode (see Table 3-7 on page 27) Forces a mute of the digital output bypass Bass / Treble / Volume matrix
PRELIMINARY DATA SHEET
3.6.1. DC/DC Converter The DCCF Register controls both the internal voltage monitor and DC/DC converter. Between output voltage of the DC/DC converter and the internal voltage monitor threshold an offset exists which is shown in the following table. Please pay attention to the fact, that I2C protocol is working only if the processor is active (WSEN = 1). However, the setting for the DCCF register will remain active if the DCEN and WSEN lines are deasserted
Default $08000 $0
Read back the PIO pin levels. The PI0 pin corresponds to bit 0 in the PIOData register. This register can be used to detect the actual state of the PIO pins, regardless of the PIO configuration. Shadows the start-up configuration set via PIO pins or I2C command (valid are bits 8, 4...0 as described in Table 2-8. responsible for prescale of the tone filter (prevent overflows) (see Section 3.6.3. on page 28) responsible for increase / decrease of low frequencies (see Section 3.6.3. on page 28) responsible for increase / decrease of high frequencies (see Section 3.6.3. on page 28) $80000 $0 $0
$e6 $e7 $6b $6f
r/w r/w r/w r/w
StartupConfig KPrescale KBass KTreble
1) In order to get the right information of the PIO pin levels (except for PI19, Demand Pin), register $ed should be read and evaluated. However, the Demand Pin PI19 is shadowed in bit 19 of register $c8.
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PRELIMINARY DATA SHEET
MAS 3507D
Table 3-7: DC/DC-converter switch frequency (Bits 8, 13..10 of DCCF-register) DCCF Value (hex)1) Bit 8 = 0 0CC00 0C800 0C400 0C000 04C00 04800 04400 04000 01C00 01800 01400 01000 00C00 00800 00400 00000
1) All
Table 3-8: DC Converter Output Voltages (Bits 16..14, Bit 9 of DCCF-register) DCCF Value (hex)1) DC/DC Converter Output 3.5 V 3.4 V 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2,8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V Internal Voltage Monitor 2) 3.3 V 3.2 V 3.1 V 3.0 V 2.9 V 2,8 V 2.7 V 2.6 V 2.5 V 2.4 V 2.3 V 2.2 V 2.1 V 2.0 V 1.9 V 1.8 V
fSW Bit 8 = 1 238 kHz 245 kHz 253 kHz 263 kHz 272 kHz 283 kHz 295 kHz 307 kHz 320 kHz 335 kHz 351 kHz 368 kHz 387 kHz 409 kHz 433 kHz 460 kHz
156 kHz 160 kHz 163 kHz 167 kHz 171 kHz 175 kHz 179 kHz 184 kHz 188 kHz 194 kHz 199 kHz 204 kHz 210 kHz 216 kHz 223 kHz 230 kHz
1C000 18000 14000 10000 0C000 08000 04000 00000 1C200 18200 14200 10200 0C200 08200 04200 00200
1) 2)
other bits are set to zero (DC/DC-converter output voltage = 3.0 V)
All other bits are set to zero (fSW = 230 kHz) PUP signal becomes inactive when output below
The DC/DC converter may generate interference noise that could be unacceptable for some applications. Thus the oscillator frequency may be adjusted in 16 steps in order to allow the system controller to select a base frequency that does not interfere with an other application. The CLKI input provides the base clock fCKLI for the frequency divider whose output is made symmetrical with an additional divider by two. The divider quotient is determined by the content of the DCCF register. This register allows 32 settings generating a DC/DC converter clock frequency fdc between: f CKLI f SW = -----------------------2 (m + n)
n {0, 15} , m { 16, 32 }
(EQ 3)
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3.6.2. Muting / Bypass Tone Control Address $aa R/W r/w Name Mute / Bypass Tone Control 0 1 2 Comment Forces a mute of the digital output no mute, Tone control active mute output, but continue decoding bypass Bass / Treble / Volume matrix
PRELIMINARY DATA SHEET
Default $0
To enable fast and simple mute functionality, set bit 0 in register $aa to `1'. Writing a `0' deactivates mute. It is possible to bypass the complete bass / treble / volume control by setting bit 1 in register $aa (write a `2'). Resetting bit 1 to `0' enables tone control again.
3.6.3. Bass and Treble Control Address $e7 $6b $6f R/W r/w r/w r/w Name KPrescale KBass KTreble Comment responsible for prescale of the tone filter (prevent overflows) (see Section 2.4.3. on page 8) responsible for increase / decrease of low frequencies (see Section 2.4.3. on page 8) responsible for increase / decrease of high frequencies (see Section 2.4.3. on page 8) Default $80000 $0 $0
Tone control is implemented in the MAS 3507D. It allows the control of bass and treble in a range up to 15 dB, as Table 3-9 shows. To prevent overflow or clipping effects, the prescaler is built-in. The prescaler decreases the overall gain of the tone filter, so the full range up to +15 dB is usable without clipping.
To select a special setting, max. 3 coefficients have to be written into registers of the MAS 3507D. This has to be done via the `write register' I2C command (see Section 3.3.3.).
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PRELIMINARY DATA SHEET
MAS 3507D
Table 3-9: Tone control registers Boost in dB +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 Bass (Reg. $6b) $61800 $5d400 $58800 $53800 $4e400 $48800 $42800 $3c000 $35800 $2e400 $27000 $1f800 $17c00 $10000 $800 0 $f7c00 $efc00 $e8000 $e0400 $d8c00 $d1800 $ca400 $c3c00 $bd400 $b7400 $b1800 $ac400 $a7400 $a2800 $9e400 Treble (Reg. $6f) $5f800 $58400 $51800 $49c00 $42c00 $3c000 $35400 $2ec00 $28400 $22000 $1c000 $16000 $10400 $ac00 $5400 0 $fac00 $f5c00 $f0c00 $ec000 $e7e00 $e2800 $de000 $d9800 $d5000 $d0400 $cbc00 $c6c00 $c1800 $bb400 $b2c00 Prefactor (Reg $e7) $e9400 $e6800 $e3400 $dfc00 $dc000 $d7800 $d25c0 $cd000 $c6c00 $bfc00 $b8000 $af400 $a5800 $9a400 $8e000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000 $80000
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3.7. Memory Area 3.7.1. Status Memory
PRELIMINARY DATA SHEET
The memory cells given in the following table should be accessed by the `read control interface data' I2C command (see Section 3.3.2. on page 21) because only the 16 LSBs of these memory blocks are used. The memory area table is a consecutive memory block in the D0 memory that keeps all important status information that monitors the MPEG decoding process. The `read control interface data' command resets the MPEG-FRAME-SYNC at PI4 as described in Section 2.9. Table 3-10: Status Memory Area Address D0:$300 D0:$301 D0:$302 D0:$303 D0:$304 D0:$305 ... $321 Offset1) 0 1 2 3 4 5 R/W r r r r r r Name MPEGFrameCount MPEGStatus1 MPEGStatus2 CRCErrorCount NumberOfAncillaryBits AncillaryData Function counts the MPEG frames MPEG header / status information MPEG header counts CRC errors during MPEG decoding number of bits in ancillary data organized in words a 16 bit (MSB first)
1) Offset applies to the `read control interface data' command
3.7.1.1. MPEG Frame Counter Address D0:$300 Offset 0 R/W r Name MPEGFrameCount Function counts the MPEG frames
The counter will be incremented with each new frame that is decoded. With an invalid MPEG bit stream as its input (e.g. if an invalid header is detected), the MAS 3507D resets the MPEGFrameCount cell to `0'. The MPEGFrameCount is also returned by the `default read' command as described in Section 3.3.9.
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PRELIMINARY DATA SHEET
MAS 3507D
3.7.1.2. MPEG Status 1 Address D0:$301 Offset 1 R/W r Name MPEGStatus 1 Function MPEG header / status information
The MPEG Status 1 contains the bits 15...11 of the MPEG header and some status bits. It will be set each frame, directly after the header has been decoded from the bit stream.
Table 3-11: MPEG Status 1 Bits 19, 15 14, 13 Name/Value %xxxx.x MPEG ID %00 %01 %10 %11 12, 11 Layer %00 %01 %10 %11 10 9...2 1 0 %1 %1 %1 Comment don't care Bits 11, 12 of the MPEG-header MPEG 2.5 reserved MPEG 2 MPEG 1 Bits 13, 14 of the MPEG-header reserved Layer 3 Layer 2 Layer 1 (Not supported) not protected by CRC private bits CRC Error invalid frame
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3.7.1.3. MPEG Status 2 Address D0:$302 Offset 2 R/W r Name MPEG Status 2 Function MPEG header
PRELIMINARY DATA SHEET
The MPEG Status 2 contains the 16 LSBs of the MPEG header. It will be set directly after synchronizing to the bit stream. Table 3-12: MPEG Status 2 Bits 19, 16 15...12 Bit rate index Value/Name Comment don't care MPEG 1 (Layer 2) in kbit/s free 32 48 56 64 80 96 112 128 160 192 224 256 320 384 forbidden MPEG 1 44.1 kHz 48 kHz 32 kHz reserved MPEG 1 (Layer 3) in kbit/s free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 forbidden MPEG 2 22.05 kHz 24 kHz 16 kHz reserved MPEG 2 in kbit/s (Layer 2 & 3) MPEG 2.5 in kbit/s free 8 16 24 32 40 48 56 64 80 96 112 128 144 160 forbidden MPEG 2.5 11.025 kHz 12 kHz 8 kHz reserved
%0000 %0001 %0010 %0011 %0100 %0101 %0110 %0111 %1000 %1001 %1010 %1011 %1100 %1101 %1110 %1111 11, 10 Sampling frequency %00 %01 %10 %11 9 8 7, 6 Padding bit Private bit Mode %00 %01 %10 %11 5, 4 Mode extension (if joint stereo only) %00 %01 %10 %11 3 %0 / 1
stereo joint_stereo (intensity stereo / ms_stereo) dual channel single_channel intensity stereo off on off on ms_stereo off off on on
copyright not protected / copyright protected
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PRELIMINARY DATA SHEET
MAS 3507D
Table 3-12: MPEG Status 2 Bits 2 1, 0 Value/Name %0 / 1 Emphasis %00 %01 %10 %11 Comment copy / original indicates the type of emphasis none 50/15 s reserved CCITT J.17
3.7.1.4. CRC Error Counter Address D0:$303 Offset 3 R/W r Name CRCErrorCount Function counts CRC errors during MPEG decoding
The counter will be increased by each CRC error in the MPEG bit stream. It will not be reset by losing the synchronization.
3.7.1.5. Number Of Ancillary Bits Address D0:$304 Offset 4 R/W r Name NumberOfAncillaryBits Function number of bits in ancillary data
This cell displays the number of valid ancillary bits stored beginning at D0:$305.
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MAS 3507D
3.7.1.6. Ancillary Data Address D0:$305 ... D0:$321 Offset 5 R/W r Name AncillaryData Function
PRELIMINARY DATA SHEET
organized in words a 16 bit (MSB first)
This memory field contains the ancillary data. It is organized in words 16 bit each. The last ancillary bit transmitted in a frame is placed at bit 0 in D0:$305. The position of the first ancillary data bit is locatable via the content of NumberOfAncillaryBits. An example: 17 bits ancillary data in a frame: A possible `read ancillary data' algorithm would read the NumberOfAncillaryBits and the complete ancillary data area using the telegram:
<$3a><$68><$31><$1e> (offset=4, n=30) <$3a><$69><$3b>
For reducing the I2C protocol transfer traffic, it may be useful to split up the `read ancillary data' algorithm into a first part that reads NumberOfAncillaryBits and a second that reads only NumberOfAncillaryBits/16+1 words. Table 3-13: Ancillary data bit assignment
D0: $305 ancillary data 15 MSB bit 1 14 bit 2 13 bit 3 12 bit 4 11 bit 5 10 bit 6 09 bit 7 08 bit 8 07 bit 9 06 bit 10 05 bit 11 04 bit 12 03 bit 13 02 bit 14 01 bit 15 00 LSB bit 16
Table 3-14: Ancillary data bit assignment
D0: $306 ancillary data 15 MSB x 14 x 13 x 12 x 11 x 10 x 09 x 08 x 07 x 06 x 05 x 04 x 03 x 02 x 01 x 00 LSB bit 0
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PRELIMINARY DATA SHEET
MAS 3507D
3.7.2. Configuration Memory The configuration memory allows the controller advanced configuration possibilities, e.g. changing setups for the crystal frequency or changing the digital format of the serial audio output data interface. Table 3-15: Configuration memory area1) Address D0:$36d D0:$36e D0:$36f D1:$7f8 D1:$7f9 D1:$7fa D1:$7fb R/W r/w r/w r/w r/w r/w r/w r/w Name PLLOffset48 PLLOffset44 OutputConfig LL LR RL RR Function PLL offset (if fs = 48, 24, 12, 32, 16, or 8 kHz), validate by `run $475' command PLL offset (if fs = 44.1, 22.05, 11.025 kHz), validate by `run $475' command Configuration of the I2S audio output interface validate by `run $475' command Left Left Gain Left Right Gain Right Left Gain Right Right Gain $80000 0 0 $80000 Default
1) Important note: Writing into undocumented memory cells is always possible, but it is highly recommended not to do so. It may damage the function of the firmware and may even lead to a complete system crash of the decoder operation which can only be restored by a reset.
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MAS 3507D
3.7.2.1. PLL Offset for 44/48 kHz Sampling Frequency Address D0:$36d D0:$36e R/W r/w r/w Name PLLOffset48 PLLOffset44 Function
PRELIMINARY DATA SHEET
Default
PLL offset (if fs = 48, 24, 12, 32, 16, or 8 kHz), validate by `run $475' command PLL offset (if fs = 44.1, 22.05, 11.025 kHz), validate by `run $475' command
With these memory cells it is possible to choose other frequencies than the standard CLKI frequencies. Please note: - PLLOffset48 is valid for fs = 48, 24, 12, 32, 16, or 8 kHz. - PLLOffset44 is valid for fs = 44.1, 22.05, 11.025 kHz. Table 3-16 shows the default values which will be set by the firmware according to the start-up configuration. Table 3-16: PLLOffset48 and PLLOffset44 fCLKI 14.725 MHz PLLOffset48 0.351986 PLLOffset44 -0.732862
Table 3-17: fClkI for max./ min. PLLOffsets PLLOffset fCLKI for fs related to 48 kHz 16.0365 MHz 14.309 MHz fCLKI for fs related to 44.1 kHz 14.7336 MHz 13.1465 MHz
-0.74 0.74
Example: A very common crystal frequency is 14.31818 MHz (NTSC color subcarrier). The ----------------------PLLOffset48 = 24,576 8 - 13 = 0,7314 14,31818 and
It is also possible to run the MAS 3507D with other clocks. In broadcast mode, it is necessary to adjust the PLLOffsets to this clock, otherwise it will not lock to the MPEG bit stream. In multimedia mode, it is recommended to adjust the PLLOffsets to the crystal, otherwise it would result in a frequency shift (music will be played faster or slower). For adjusting, the following procedure must be done: - Calculate the PLLOffsets according to: 24,576 8 22,5792 8 f CLKI = --------------------------------------------- = --------------------------------------------13 + PLLOffset48 13 + PLLOffset44 with -0.74 < PLLOffset < 0.74. This corresponds to a frequency range of 14.31...14.73 MHz for the crystal, if both 44.1 kHz and 48 kHz based sample frequencies are used. The range is extended in an application with a fixed sampling frequency, as Table 3-17 shows. - Write the PLLOffsets to the memory (PLLOffset48 D0:$36d, PLLOffset44 D0:$36e). - Send a `run $475' command. With the jump to this address, the settings in the memory will be valid for the internal processing.
-------------------------PLLOffset44 = 22,5792 8 - 13 = - 0,3843 14,31818 are inside the range -0.74 ... 0.74.
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PRELIMINARY DATA SHEET
MAS 3507D
3.7.2.2. Output Configuration Address D0:$36f R/W r/w Name OutputConfig Function Configuration of the I2S audio output interface validate by `run $475' command Default
The content of this memory cell depends on the startup configuration and will be set by the firmware. Nevertheless, the audio output interface is configurable by the software to work in different 16 bit/sample modes and 32 bit/sample modes (see Section 2.7.4. on page 13). For adjusting to this, the following procedure has to be done: - Choose the output mode (see Table 3-18). - Write this value to the memory (D0:$36f). - Send a `run $475' command. With the jump to this address, the settings in the memory will become valid for the internal processing. This overrides all start-up settings
Table 3-18: Output Configuration Bits 19...15 14 Value %0000.0 %0 %1 Comment don't care SOC standard timing SOC inverted timing don't care no delay additional delay of data related to word strobe don't care not invert invert outgoing word strobe signal 32 bits/sample 16 bits/sample don't care
13..12 11
%00. %0 %1
3.7.3. Baseband Volume Matrix 10...6
Address D1:$7f8 D1:$7f9 D1:$7fa D1:$7fb R/W r/w r/w r/w r/w Name LL LR RL RR Function Left->Left gain Left->Right gain Right->Left gain Right->Right gain Default $80000 $0
%000.00 %0 %1 %0 %1 %0000
5
4
$0 $80000
3...0
The digital Baseband volume Matrix is used for controlling the digital gain and a simple kind of stereo basewidth enlargement as shown in Fig. 3-2. Table 3- 20 shows the proposed settings for the 4 volume matrix coefficients for stereo, left and right mono. The gain factors are given in fixed point notation. The gain values may be written to the MAS 3507D by the controller command 'write D1 memory'.
Table 3-19: Bit Assignment of the Volume Cells Bits 19..0 Name Value LL/LR/RL/RR Comment -524288/524288..524287/524288 = -1.0 .. 1.0 - 2^-19
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MAS 3507D
PRELIMINARY DATA SHEET
Table 3-20: Settings for the digital volume matrix left audio -1 LL + Memory location Name -1 LR Stereo (default) Mono left -1 RL Mono right D1: $7f8 LL -1.0 -1.0 0 D1: $7f9 LR 0 -1.0 0 D1: $7fa RL 0 0 -1.0 D1: $7fb RR -1.0 0 -1.0
right audio
-1
RR
+
The fixed point gain values correspond to 20 bit 2's complement notation. The conversion between fixed point and 2's complement notation is done easily by the algorithms described in Section 3.2.1.
Fig. 3-2: Digital volume matrix
Table 3-21: Volume matrix conversion (dB into hexadecimal) Volume (in dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 Hexa decimal 80000 8DEB8 9A537 A5621 AF3CD B8053 BFD92 C6D31 CD0AD D2958 D785E DBECC DFD91 E3583 E675F E93CF EBB6A EDEB6 EFE2C F1A36 Volume (in dB) -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 Hexa decimal F3333 F4979 F5D52 F6F03 F7EC8 F8CD5 F995B FA485 FAE78 FB756 FBF3D FC648 FCC8E FD227 FD723 FDB95 FDF8B FE312 FE638 FE905 Volume (in dB) -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 Hexa decimal FEB85 FEDBF FEFBB FF180 FF314 FF47C FF5BC FF6DA FF7D9 FF8BC FF986 FFA3A FFADB FFB6A FFBEA FFC5C FFCC1 FFD1B FFD6C FFDB4 Volume (in dB) -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 Hexa decimal FFDF4 FFE2D FFE60 FFE8D FFEB5 FFED9 FFEF9 FFF16 FFF2F FFF46 FFF5A FFF6C FFF7C FFF8B FFF97 FFFA3 FFFAD FFFB6 FFFBE FFFC5 Volume (in dB) -80 -81 -82 -83 -84 -85 -86 -87 -88 -89 -90 -91 -92 -93 -94 -95 -96 -97 -98 -99 Hexa decimal FFFCC FFFD1 FFFD6 FFFDB FFFDF FFFE3 FFFE6 FFFE9 FFFEB FFFED FFFEF FFFF1 FFFF3 FFFF4 FFFF6 FFFF7 FFFF8 FFFF9 FFFF9 FFFFA
Table 3-21 contains the converted gain values as used in the 'write D1 memory' command
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PRELIMINARY DATA SHEET
MAS 3507D
4. Specifications 4.1. Outline Dimensions
0.9 0.2
1.1 x 45 6 7 1.6 17.52 0.12 2 5 1 40 39 0.48 0.06
10 x 1.27 = 12.7 0.1 1.27 1.2 x 45
0.71 0.05
15.7 0.3
16.5 0.1
2
5
8.6
17 18 17.52 0.12 28
29 1.9 0.05 4.05 0.1 4.75 0.15
0.28 0.04
0.1
16.5 0.1
SPGS0027-2(P44/K)/1E
Fig. 4-1: 44-Pin Plastic Leaded Chip Carrier Package (PLCC44) Weight approximately 2.5 g Dimensions in mm
10 x 0.8 = 8 0.1 0.17 0.06 33 34 13.2 0.2 23 22 10 0.1 0.8 0.8
1.3 12 1 1.75 13.2 0.2 2.15 0.2 11
1.75
44
2.0 0.1 0.1 10 0.1
0.375 0.075
SPGS706000-2(P44)/1E
Fig. 4-2: 44-Pin Plastic Quad Flat Package (PMQFP44) Weight approximately 0.4 g Dimensions in mm
Note: Start pin and orientation of pin numbering is different for PLCC and PMQFP packages!
Micronas
10 x 0.8 = 8 0.1
10 x 1.27 = 12.7 0.1
1.27
39
MAS 3507D
PRELIMINARY DATA SHEET
A1 Ball Pad Corner 7 6 5 4 3 21
1.4 0.36
A B 6 x 0.8 = 4.8 C 0.8 D E F G 1.1 0.46 1.04
SPGS0007-1/2E
7
0.8 1.1 6 x 0.8 = 4.8 7
Fig. 4-3: 49-Ball Plastic Ball Grid Array (PBGA49) Weight approximately 0.13 g Dimensions in mm
4.2. Pin Connections and Short Descriptions NC LV X not connected, leave vacant If not used, leave vacant obligatory, pin must be connected as described in application information Pin No.
PMQFP 44-pin PLCC 44-pin PBGA 49-ball
VDD connect to positive supply VSS connect to ground
Pin Name
Test Alias in ()
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14
6 5 4 3 2 1 44 43 42 41 40 39 38 37
C3 C2 B1 D2 C1 D1 E2 E1 F2 F1 G1 E3 F3 G2
TE POR I2CC I2CD VDD VSS DCEN EOD RTR RTW DCSG DCSO VSENS PR
IN IN IN/OUT IN/OUT SUPPLY SUPPLY IN OUT OUT OUT SUPPLY OUT IN IN
VSS VDD X X X X VSS LV LV LV VSS VSS VDD X
Test Enable Reset, Active Low I2C Clock Line I2C Data Line Positive Supply for Digital Parts Ground Supply for Digital Parts Enable DC/DC Converter PIO End of DMA, Active Low PIO Ready to Read, Active Low PIO Ready to Write, Active Low DC Converter Transistor Ground DC Converter Transistor Open Drain DC Converter Voltage Sense PIO-DMA Request or Read/Write
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PRELIMINARY DATA SHEET
MAS 3507D
Pin No.
PMQFP 44-pin PLCC 44-pin PBGA 49-ball
Pin Name
Test Alias in ()
Type
Connection
(If not used)
Short Description
15 16
36 35
F4 G3
PCS PI19
IN IN/OUT
X LV
PIO Chip Select, Active Low PIO Data [19] 1. Demand Pin in SDI mode 2. data bit [7], MSB (PIO-DMA input mode) PIO Data [18] 1. MPEG header bit 11 - MPEG ID (SDI mode) 2. data bit [6] (PIO-DMA input mode) PIO Data [17] 1. MPEG header bit 12 - MPEG ID (SDI mode) 2. data bit [5] (PIO-DMA input mode) PIO Data [16] 1. SIC*, alternative input for SIC (SDI mode) 2. data bit [4] (PIO-DMA input mode) PIO Data [15] 1. SII*, alternative input for SII (SDI mode) 2. data bit [3] (PIO-DMA input mode) PIO Data [14] 1. SID*, alternative input for SID (SDI mode) 2. data bit [2] (PIO-DMA input mode) PIO Data [13] 1. MPEG header bit 13 - Layer ID (SDI mode) 2. data bit [1] (PIO-DMA input mode) PIO Data [12] 1. MPEG header bit 14 - Layer ID (SDI mode) 2. data bit [0] (PIO-DMA input mode) Serial Output Data Serial Output Frame Identification Serial Output Clock Start-up1): Clock output scaler on / off Operation2): MPEG CRC error
17
34
E4
PI18
IN/OUT
LV
18
33
G4
PI17
IN/OUT
LV
19
32
F5
PI16
IN/OUT
LV
20
31
G5
PI15
IN/OUT
LV
21
30
F6
PI14
IN/OUT
LV
22
29
G6
PI13
IN/OUT
LV
23
28
E5
PI12
IN/OUT
LV
24 25 26 27
27 26 25 24
E6 F7 D6 E7
SOD SOI SOC PI8
(PI11) (PI10) (PI9)
OUT OUT OUT IN OUT
LV LV LV X
28 29 30 31
23 22 21 20
D7 C6 C7 B6
XVDD XVSS SID SII (PI7) (PI6)
SUPPLY SUPPLY IN IN
X X X VSS
Positive Supply of Output Buffers Ground of Output Buffers Serial Input Data Serial Input Frame Identification
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PRELIMINARY DATA SHEET
Pin No.
PMQFP 44-pin PLCC 44-pin PBGA 49-ball
Pin Name
Test Alias in ()
Type
Connection
(If not used)
Short Description
32 33
19 18
B7 A7
SIC PI4
(PI5)
IN IN OUT
X X
Serial Input Clock Start-up1): Select SDI / PIO-DMA input mode Operation2): MPEG-Frame Sync
34
17
B5
PI3
IN
X
Start-up1): Enable Layer 3 / Disable Layer 3 decoding Operation2): MPEG header bit 20 (Sampling frequency)
OUT 35 16 A6 PI2 IN X
Start-up1): Enable Layer 2 / Disable Layer 2 decoding Operation2): MPEG header bit 21 (Sampling frequency)
OUT 36 15 B4 PI1 IN X
Start-up1): SDO: Select 32-bit mode / 16-bit I2S mode Operation2): MPEG header bit 30 (Emphasis)
OUT 37 14 A5 PI0 IN X
Start-up1): Select Multimedia mode / Broadcast mode Operation2): MPEG header bit 31 (Emphasis)
OUT 38 39 40 41 13 12 11 10 C4 A4 B3 A3 CLKO PUP WSEN WRDY OUT OUT IN OUT LV LV X LV
Clock Output for the D/A converter Power Up, i.e. status of voltage supervision Enable DSP and Start DC/DC Converter If WSEN = 0: valid clock input at CLKI If WSEN = 1: clock synthesizer PLL locked Supply for analog circuits Clock input Ground supply for analog circuits
42 43 44
1) 2)
9 8 7
B2 A2 A1
AVDD CLKI AVSS
SUPPLY IN SUPPLY
VDD X VSS
Start-up configuration see Section 2.8. Not available in PIO-DMA mode, see Section 2.8.1.
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PRELIMINARY DATA SHEET
MAS 3507D
4.2.1.3. Control Lines I2CC I2CD SCL SDA IN/OUT IN/OUT
4.2.1. Pin Descriptions 4.2.1.1. Power Supply Pins Connection of all power supply pins is mandatory for the function of the MAS 3507D. VDD VSS SUPPLY SUPPLY
Standard I2C control lines. Normally there are Pullupresistors tied from each line to VDD.
4.2.1.4. Parallel Interface Lines The VDD/VSS pair is internally connected with all digital modules of the MAS 3507D. XVDD XVSS SUPPLY SUPPLY 4.2.1.4.1. PIO Handshake Lines PIO handshake lines are not used during start-up but in operation mode. Read out of the status information and the demand mode work in P-mode: set PCS = '0' and PR = '1'. Usage of PIO-DMA mode is possible with input mode via PIO. PCS IN
The XVDD/XVSS pins are internally connected with the pin output buffers. AVDD AVSS SUPPLY SUPPLY
The AVDD/AVSS pair is connected internally with the analog blocks of the MAS 3507D, i.e. clock synthesizer and supply voltage supervision circuits.
The PIO chip select must be set to `0' to activate the PIO as Output in operation mode (e.g. PI19 = demand signal in mutimedia mode & SDI input mode). PR IN
4.2.1.2. DC/DC Converter Pins DCEN IN
The PIO PR must be set to `1' to validate data output from MAS 3507D. RTW OUT
The DCEN input signal enables the DC/DC converter operation. DCSG SUPPLY
RTW is not supported by the built-in firmware. RTR OUT
The DC converter Signal Ground pin is used as a basepoint for the internal switching transistor of the DC/DC converter. It must always be connected to ground. DCSO OUT
RTR is only supported by the built-in firmware in PIODMA input mode. EOD OUT
End of DMA (EOD) is only supported by the built-in firmware in PIO-DMA input mode.
DCSO is an open drain output and should be connected with external circuitry (inductor/diode) to start the DC/DC converter. When the DC/DC converter is not used, it has to be connected to VSS. VSENS IN
4.2.1.4.2. PIO Data Lines The function of the parallel interface is separated into two parts. During start-up, the PIO will read the startup configuration (independent from the PIO handshake lines). This is done to define the environment for the MAS 3507D (see Section 2.8.1. for details). After start-up, the PIO will be switched to P-mode. With the PR = `1' and the PCS = `0', the PIO interface is defined as output and displays some status information of the MPEG decoder. The PIO can be connected to an external controller or to a display unit (e.g. LED). The internal MPEG decoder firmware attaches specific functions to the following pins:
The VSENS pin is the input for the DC/DC converter feedback loop. It must be connected directly with the Schottky diode and the capacitor as shown in Fig. 2-3. When the DC/DC converter is not used, it has to be connected to VDD.
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MAS 3507D
PI19 DEMAND PIN OUT
PRELIMINARY DATA SHEET
4.2.1.5. Voltage Supervision And Other Functions CLKI IN
When MAS 3507D is in multimedia mode it demands with PI19 = '1' for new input data. PI18 PI17 MPEG-IDEX MPEG-ID OUT OUT
This is the clock input of the MAS 3507D. CLKI should be a buffered output of a crystal oscillator. Standard clock frequency is 14.725. Others can be used, if PLL_offset register is changed by I2C. CLKO OUT
These pins mirror the according bits of the MPEG header (see Table 2-9 for details). PI16 PI15 PI14 (SIC*) (SII*) (SID* IN IN IN
The CLKO is an oversampling clock that is synchronized to the digital audio data (SOD) and the frame identification (SOI). PUP OUT
The SIC*, SID*, and SII* may be configured as alternative serial input lines in order to support alternative serial digital inputs. PI13 PI12 LAYER ID LAYER ID OUT OUT
The PUP output indicates that the power supply voltage exceeds its minimal level (software adjustable). WSEN IN
These pins mirror the according bits of the MPEG header (see Table 2-9 for details). PI8 MPEG-CRC-ERROR OUT/IN
WSEN enables DSP operation and starts DC/DC-converter. WRDY OUT
The MPEG-CRC-ERROR pin is activated if no successful MPEG decoding is possible. The reason might be that the CRC check of the MPEG Frame header has detected an error or that no valid bit stream is available. The error signal will stay active for the entire duration of one MPEG frame. During start-up, this pin is an input for enabling/disabling the CLKO+divider (see Section 3.6.). PI4 MPEG-FRAME-SYNC OUT/IN
WRDY has two functions depending on the state of the WSEN signal. If WSEN = '0', it indicates that a valid clock has been recognized at the CLKI clock input. If WSEN = '1', the WRDY output will be set to `0' until the internal clock synthesizer has locked to the incoming audio data stream, and thus, the CLKO clock output signal is valid.
The MPEG-FRAME-SYNC signal indicates that a MPEG header has been decoded properly and the internal MPEG decoder is in a synched state. The MPEG-FRAME-SYNC signal is inactive after Power On Reset and will be activated if a valid MPEG Layer 2 or 3 header has been recognized. The signal will be cleared if the ancillary data information is read out by the controller via I2C interface. During start-up, this pin sets either SDI- or PIO-DMAinput mode (see Section 3.6.).
4.2.1.6. Serial Input Interface SID SII SIC IN IN IN
Data, Frame Indication, and Clock line of the serial input interface. The SII line should be connected with VSS in the standard mode.
4.2.1.7. Serial Output Interface PI3 PI2 PI1 PI0 SAMPLING FREQUENCY SAMPLING FREQUENCY EMPHASIS EMPHASIS OUT OUT OUT OUT SOD SOI SOC OUT OUT OUT
These pins mirror the according bits of the MPEG header (see Table 2-9 for details). During start-up, these pins are input pins (see Section 3.6.).
Data, Frame Indication, and Clock line of the serial output interface. The SOI indicates whether the left or the right audio sample is transmitted. Besides the two modes (selected by the PI1 during start-up), it is possible to reconfigure the interface.
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PRELIMINARY DATA SHEET
MAS 3507D
4.2.1.8. Miscellaneous POR IN
The Power On Reset pin is used to reset the digital parts of the MAS 3507D. POR is a low active signal. TE IN
The TE pin is for production test only and must be connected with VSS in all applications.
4.2.2. Pin Configurations
VSS VDD I2CD I2CC POR TE DCEN EOD RTR RTW DCSG PI4 SIC SII XVSS SID
XVDD PI8 SOC SOI SOD PI12
6 AVSS CLKI AVDD WRDY WSEN PUP CLKO PI0 PI1 PI2 PI3 7 8 9 10 11 12 13 14 15 16 17
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 DCSO VSENS PR PCS PI19 PI18 PI17 PI16 PI15 PI14 PI13 PI3 PI2 PI1 PI0 CLKO PUP WSEN WRDY AVDD CLKI AVSS 34 35 36 37 38 39 40 41 42 43 44
33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 PI13 PI14 PI15 PI16 PI17 PI18 PI19 PCS PR VSENS DCSO
MAS 3507D
34 33 32 31 30 29
MAS 3507D
17 16 15 14 13 12
18 19 20 21 22 23 24 25 26 27 28 PI4 SIC SII SID XVSS XVDD PI8 SOI SOC PI12 SOD TE
1
2
3
4
5
6
7
8
9
10 11 DCSG RTW RTR
POR I2CC I2CD VDD VSS
EOD DCEN
Fig. 4-4: 44-pin PLCC package
Fig. 4-5: 44-pin PMQFP package
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MAS 3507D
4.2.3. Internal Pin Circuits TTLIN
PRELIMINARY DATA SHEET
DCSO
DCSG Fig. 4-6: Input pins PCS, PR VSS Fig. 4-12: Input/Output pins DCSO, DCSG
VDD Fig. 4-7: Input pin TE, DCEN P
N VSS Fig. 4-8: Input pins WSEN, POR Fig. 4-13: Output pins WRDY, RTW, EOD, RTR, CLKO, PUP
VSENS
Fig. 4-9: Input pin CLKI
VDD VSS P Fig. 4-14: Input pin VSENS N VSS Fig. 4-10: Input/Output pins PI0...PI4, PI8, SOC, SOI, SOD, PI12...PI19 VDD P
N VDD VSS Fig. 4-15: Input/Output pins SIC, SII, SID N VSS Fig. 4-11: Input/Output pins I2CC, I2CD
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PRELIMINARY DATA SHEET
MAS 3507D
4.2.4. Electrical Characteristics 4.2.4.1. Absolute Maximum Ratings Symbol TA TS PMAX Parameter Ambient Operating Temperature Storage Temperature Power dissipation VDD, XVDD, AVDD VDD, XVDD, AVDD -0.3 -20 Pin Name Min. -30 -40 Max. 85 125 600 400 (PBGA) 5.5 V Unit C C mW
VSUP
Supply voltage
VIdig IIdig IOut IOutDC
Input voltage, all digital inputs Input current, all digital inputs Current, all digital output Current DCSO
VSUP +0.3 +20 0.5 1.5
V mA A A
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability.
4.2.4.2. Recommended Operating Conditions Symbol TA VSUP Parameter Ambient temperature range Supply voltage VDD, XVDD, AVDD Pin Name Min. -30 2.5 2.7 Typ. Max. 85 3.6 Unit C V
Reference Frequency Generation CLKF CLKI_V CLKAmp
1)
Clock Frequency1) Clock Input Voltage Clock Amplitude
CLKI 0 0.5
14.725 VSUP
MHz V Vpp
range acc. to Section 3.7.2.1.
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MAS 3507D
PRELIMINARY DATA SHEET
Symbol Levels IIL27 IIH36 IIH33 IIH30 IILD IIHD
Parameter
Pin Name
Min.
Typ.
Max.
Unit
Input Low Voltage @VSUP = 2.5 V ... 3.6 V Input High Voltage @VSUP = 2.5 V ... 3.6 V Input High Voltage @VSUP = 2.5 V ... 3.3 V Input High Voltage @VSUP = 2.5 V ... 3.0 V Input Low Voltage Input High Voltage
POR I2CC, I2CD, DCEN, WSEN
0.4 1.8 1.7 1.6
V V V V
PI2), SII, SIC, SID, PR, PCS, TE, PI, SII, SIC, SID, PR, PCS, CLKI SIC, CLKI
0.4 VSUP- 0.5
V V
Trf
Rise / Fall time of digital inputs
10
ns
Dcycle
Duty cycle of digital clock inputs
40
50
60
%
DC-DC converter external circuitry C1 VF L
2) 3) 4) 5)
Blocking Capacitor (25 m ESR)3) Schottky Diode Forward voltage4) Inductance of Ferrite ring core coil5) (50 m),VAC 616/103
VSENS, DCSG DCSO, VSENS DCSO 0.35
330 0.45 20
F V H
i = 0 to 4, 8 , 12 to 19 Sanyo Oscon 6SA330M (distributed by Endrich Bauelemente, D-72202 Nagold-lselshausen, www.endrich.com) ZETEX ZMCS1000 (distributed by ZETEX, D-81673 Munchen, europe.sales@zetex.com), standard Schottky 1N5817 C8 R/4L, SDS0604 (distributed by Endrich Bauelemente, see above)
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Micronas
PRELIMINARY DATA SHEET
MAS 3507D
4.2.4.3. Characteristics at TA = -30 to 85 C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty cycle = 50%
Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
Supply Voltage ISUP Current consumption VDD, XVDD, AVDD 32 17 11 Digital Outputs and Inputs VDOL VDIH Output Low Voltage Output High Voltage SOI1), SOC1), SOD1), EOD, RTR, RTW, WRDY, PUP, CLKO PI PI, SII, SIC, SID, PR, PCS, CLKI 0.3 VSUP- 0.3 V V Iload = 6mA Iload = 6mA mA mA mA 2.7 V, sampling frequency 32kHz 2.7 V, sampling frequency 24 kHz 2.7 V, sampling frequency 12 kHz
ZDigI IDLeak
Input Impedance Digital Input Leakage Current
7 -1 1
pF A 0 V < Vpin < VSUP
1)
in low inpedance mode
Micronas
49
MAS 3507D
4.2.4.3.1. I2C Characteristics
PRELIMINARY DATA SHEET
at TA = -30 to 85 C, VSUP =2.5 to 3.6 V, typ. values at TA = 27C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol RON fI2C tI2C1 tI2C2 tI2C3 tI2C4 tI2C5 tI2C6 VI2COL II2COH tI2COL1 tI2COL2 Parameter Output resistance I2C Bus Frequency I2C START Condition Setup Time I2C STOP Condition Setup Time I2C Clock Low Pulse Time I2C Clock High Pulse Time I2C Data Hold Time before rising edge of clock I2C Data Hold Time after falling edge of clock I2C Output Low Voltage I2C Output high leakage current I2C Data Output Hold Time after falling edge of clock I2C Data Output Setup Time before rising edge of clock Pin Name I2CC, I2CD I2CC I2CC, I2CD I2CC, I2CD I2CC I2CC I2CC I2CC I2CC, I2CD I2CC, I2CD I2CC, I2CD I2CC, I2CD 20 250 300 300 1250 1250 80 80 0.3 1 Min. Typ. Max. 60 400 Unit kHz ns ns ns ns ns ns V uA ns ns fI2C = 400kHz ILOAD = 5 mA VI2CH = 3.6 V Test Conditions Iload = 5 mA, VSUP = 2.7 V
1/fI2C tI2C4
H L
tI2C3
I2CC tI2C1 tI2C5 tI2C6 tI2C2
H L
I2CD as input tI2COL2 tIC2OL1
H L
I2CD as output
Fig. 4-16: I2C timing diagram
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Micronas
PRELIMINARY DATA SHEET
MAS 3507D
4.2.4.3.2. I2S Bus Characteristics - SDI at TA = -30 to 85 C, VSUP =2.5 to 3.6 V, typ. values at TA = 27C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol tSICLK tSIIDS tSIIDH tbw Parameter I2S Clock Input Clockperiod I2S Data SetupTime before falling edge of clock I2S data hold time Burst wait time Pin Name SIC SIC, SID SID SIC, SID Min. 960 50 50 480 tSICLK100 Typ. Max. Unit ns ns ns Test Conditions multimedia mode, mean data rate < 150 kbit/s
TSICLK H
SIC
L
H
(SII)
L
H
SID
L TSIIDS TSIIDH
Fig. 4-17: Serial input
Micronas
51
MAS 3507D
4.2.4.3.3. I2S Characteristics - SDO
PRELIMINARY DATA SHEET
at TA = -30 to 85 C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol tSOCLK tSOISS tSOODC Parameter I2S Clock Output Period I2S Wordstrobe Hold Time after falling edge of clock I2S Data Hold Time after falling edge of clock Pin Name SOC SOC, SOI SOC, SOD 10 10 Min. Typ. 325 tSOCLK/ 2 tSOCLK/ 2 Max. Unit ns ns ns Test Conditions 48 kHz Stereo 32 bit/sample
TSOCLK H
SOC
L
H
SOI
L TSOISS H TSOISS
SOD
L TSOODC
Fig. 4-18: Serial output
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Micronas
PRELIMINARY DATA SHEET
MAS 3507D
4.2.4.4. Firmware Characteristics at TA = -30 to 85 C, VSUP = 2.5 to 3.6 V, typ. values at TA = 27C, VSUP = 2.7 V, CLKF = 14.725 MHz, duty cycle = 50 %
Symbol Parameter Min. Typ. Max. Unit Test Conditions
Synchronization Times tmpgsync Ranges PLLRange Tracking range of sampling clock recovery PLL -200 200 ppm Broadcast mode Synchronization on MPEG Bit Streams 12...36 72 ms fs = 32 kHz, MPEG 2.5
4.2.4.4.1. Input Timing Parameters of the MultimediaMode
Symbol Tsdstart Tsdstart Tsdstar Tsdstar Tsdstop Parameter Reaction time for data source Reaction time for data source Reaction time for data source Reaction time for data source Reaction time for data source Pin Name PI19 Min. 3.1 4.2 23.1 34.8 Typ. Max. 5.7 9.2 25.6 38.4 1.3 Unit ms ms ms ms ms Test Conditions fs = 48 kHz, 320...64 kbit/s fs = 24 kHz, 320...32 kbit/s fs = 12 kHz, 64...16 kbit/s fs = 8 kHz, 64...8 kbit/s
H
PI19
L Tsdstart Tsdstop
Fig. 4-19: Demand mode
Tsdstart refers to the maximal response time for a serial data source to start data transmission with respect to the rising edge of the demand signal at the pin PI19. Tsdstop refers to the maximal response time for a serial data source to stop data transmission with respect to the falling edge of the demand signal at the pin PI19.
Micronas
53
MAS 3507D
4.2.4.5. DC/DC Converter Characteristics
PRELIMINARY DATA SHEET
at TA = -30 to 85 C, VSUP = 3.0 V, CLKF = 14.725 MHz, fsw = 230 kHz, typ. values at TA = +27 C
Symbol VIN1 Parameter Minimum Start-Up Input Voltage Minimum Operating Voltage Pin Name Min. Typ. 0.9 Max. 1.0 Unit V Test Conditions ILOAD = 0 mA DCCF = $08000 (Reset) ILOAD = 55 mA, DCCF = $08000 (Reset) ILOAD = 250 mA, DCCF = $08000 (Reset) see Section 4.2.4.6. VIN = 1.0...3.0 V, ILOAD = 55 mA VIN = 1.2 V, ILOAD = 0...55 mA, fSW = 230 kHz VIN = 1.2 V, ILOAD = 0...55 mA, fSW = 165 kHz
VIN2
0.6
0.8
V
1.3
1.8
V
VOUT dVOUT/dVIN/ VOUT dVOUT/dILOAD/ VOUT dVOUT/dILOAD/ VOUT hmax ISUPPLY IL,MAX RON ILEAK fSW tSTART
Output Voltage Line Regulation Load Regulation
2.0 1) 1 0.6
3.5
V % %
Load Regulation
1.2
%
Maximum Efficiency Supply Current Inductor Current Limit Switch On-Resistance Switch Leakage Current Switch Frequency Start Up Time to PUP-Enable DCSO, DCSG DCSO, DCSG DCSO, DCSG DCSO, DCSG DCEN, PUP VSENSE 156
90 1.1 1.0 0.2 0.1 230 8 5 1.4 0.4 1 460
% mA A A kHz ms Tj = 25 C Tj = 25 C Depending on DCCF VIN = 1.0 V, ILOAD = 1 mA, PUPLIM = 010 (Reset) VIN = 3.0 V, ILOAD = 0, includ. switch current
VSTARTTRAN
Start-Up to Normal Mode Transition Voltage
1.9
V
1) see Section 4.2.4.2.
All measurements are made with a C8 R/4L 20 H, 25 m ferrite ring-core coil, Zetex ZLMCS1000 Schottky diode, and Sanyo/Oscon 6SA330M 330 F, 25 m ESR capacitors at input and output (see Section 4.2.4. on page 47).
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Micronas
PRELIMINARY DATA SHEET
MAS 3507D
4.2.4.6. Typical Performance Characteristics
Efficiency vs. Load Current (Vout=3.5V) 100
3.0 V 1.8 V
Efficiency vs. Load Current (Vout=3.0V) 100
2.4 V
80
Vin
80
Vin
Efficiency (%)
Efficiency (%)
60
60
0.7 V
40 Vin: 3.0V 2.4V 1.8V 10 -4 10-3 10-2 10-1 1
40
20
20
Vin: 2.4V 1.8V 1.5V 1.2V 0.9V 0.7V 10 -4 10-3 10-2 10-1 1
0
0 Load Current (A)
Load Current (A)
Efficiency vs. Load Current (Vout=2.7V) 100
Vin 2.4 V
Efficiency vs. Load Current (Vout=2.2V) 100
Vin 1.5 V
80
1.2 V
80
Efficiency (%)
Efficiency (%)
60
60
0.7 V
40 Vin: 2.4V 1.8V 1.2V 0 10 -4 10-3 10-2 10-1 1 Load Current (A)
40 Vin: 1.5V 1.2V 0.9V 0.7V 10 -4 10-3 10-2 10-1 1
20
20
0 Load Current (A)
Fig. 4-20: Efficiency vs. Load Current
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
Output Voltage vs. Input Voltage Iload=250mA 3.6
3.5 V
Output Voltage vs. Input Voltage Iload=50mA 3.2
3.1 V
3.4
3
2.8 Output Voltage (V) Output Voltage (V) 3.2
3.1 V 2.7 V
2.6
3
2.4
2.2 V
2.8
2.7 V
2.2
2.6 1.5 2 2.5 3 3.5 Input Voltage (V)
Fig. 4-21: Output Voltage vs. Input Voltage
2 0.9 1.4 1.9 2.4 2.9 Input Voltage (V)
Output Voltage vs. Load Current 3.6
Vin
Output Voltage vs. Load Current 3.4
3.4
Vin=3V, 2.4V, 1.8V
3.2 3 Vin=1.5V, 0.9V
Vin
Output Voltage (V)
Output Voltage
3.2
2.8 2.6 2.4
Vin
3
2.8 2.2 2.6 0 Vin=2.4V 0.1 0.2 0.3 Vin=1.5V, 0.9V 2 0 0.02 0.04 0.06 0.08 Load Current (A)
Load Current (A)
Fig. 4-22: Output Voltage vs. Load Current
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Micronas
PRELIMINARY DATA SHEET
MAS 3507D
0.8 Maximum Load Current (A)
Maximum Load Current vs. Input Voltage 6.0
No Load Supply Current vs. Input Voltage
0.6 2.2V 0.4
Vout
No Load Supply Current (mA)
3.5V
Vout = 3 V
4.0
0.2
Vout= 3.5V 3.1V 2.7V 2.2V
2.0
0 0 1 2 Input Voltage (V) 3
0 0 1 2 3 Input Voltage (V)
Fig. 4-23: Maximum Load Current vs. Input Voltage
Fig. 4-24: No Load Supply Current vs. Input Voltage
Micronas
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MAS 3507D
PRELIMINARY DATA SHEET
3V 3V
3V
3V 0A
0A 0A
500.00 s/Div Vin = 1.2 V; Vout = 3 V 1 Load Current 2 Output Voltage 3 Inductor Current 200.0 mA/Div 100.0 mV/Div / AC-coupled 500.0 mA/Div 1 2 3 4 V (DCEN) V (PUP) Inductor Current Output Voltage
500 s/Div Vin = 1 V; Iload = 0 mA 2.000 V/Div 2.000 V/Div 500.0 mA/Div 2.000 V/Div
Fig. 4-25: Load Transient-Response
Fig. 4-27: Startup Waveform
3V
2V
5.00 ms/Div Iload = 100 mA; Vout = 3 V 2.000 V/Div 1 Vin 2 Output Voltage 50.00 mV/Div / AC-coupled 3 Inductor Current 200.0 mA/Div Fig. 4-26: Line Transient-Response
58
200 mA
Micronas
PRELIMINARY DATA SHEET
MAS 3507D
Micronas
59
MAS 3507D
5. Data Sheet History 1. Preliminary data sheet: "MAS 3507D MPEG 1/2 Layer2/3 Audio Decoder", Feb. 25, 1998, 6251-459-1PD. First release of the preliminary data sheet. 2. Preliminary data sheet: "MAS 3507D MPEG 1/2 Layer 2/3 Audio Decoder", Oct. 21, 1998, 6251-459-2PD. Second release of the preliminary data sheet. Major changes: - Table 3-20: Volume matrix conversion added - Address for Prefactor register corrected - Definition for register $aa changed - Fig. 4-1: Outline Dimension for PLCC44 changed - Fig. 4-2: PQFP44 package diagram changed - Fig. 4-3 and Fig. 4-4: Pin configurations added 3. Preliminary data sheet: "MAS 3507D MPEG 1/2 Layer 2/3 Audio Decoder, March 16, 2000, 6251-459-3PD. Third release of the preliminary data sheet.
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-459-3PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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Micronas

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